1. Field of the Invention
The present invention relates to the fabrication of integrated circuits, and, more particularly, to implanting ions of dopant materials into workpieces and/or substrates suitable for the fabrication of integrated circuits as are employed, for example, in the formation of so-called “halo” structures of field effect transistors.
2. Description of the Related Art
In the last several years, the numbers of circuit elements manufacturable on semiconductor substrates has continuously grown. For example, in modern integrated circuit devices, there may be approximately one billion elements per chip due to the continuing miniaturization of feature sizes. Presently, circuit elements are commonly fabricated featuring minimum sizes less than 0.18 μm and the progress in the manufacturing technology seems likely to continue to proceed in this manner.
In the particular case of field effect transistors, the increasing density of the transistors manufacturable on a substrate, together with a corresponding miniaturization of the transistors, results in a reduced channel length and width. However, as process technology improved to the point where devices could be fabricated with a gate length less than 2 μm, it turned out that MOSFETs began to exhibit phenomena not predicted by the MOSFET models. Such phenomena are termed short-channel effects and have a severe influence on, among others, transistor characteristics, such as threshold voltage, drain-induced-barrier-lowering, sub-surface punch-through in NMOSFETS and punch-through in PMOSFETS.
Of these short-channel effects, punch-through in MOSFETs revealed to be the one that most affects the reliability of MOSFETs. Punch-through is a phenomenon associated with the merging of the source and drain depletion regions in the MOSFET. That is, for a constant channel-region doping, as the channel gets shorter, the distance between the depletion region edges is reduced. When the channel length is decreased to roughly the sum of the two junction depletion widths, a punch-through condition is established. Once punch-through occurs, any further increase in the applied reverse-bias drain voltage will lower the potential energy barrier for majority carriers in the source. With a diminished barrier height, a larger number of majority carriers in the source region have enough energy to be injected from the source to the substrate. Some of these injected electrons are collected by the drain, causing the sub-threshold drain current to increase. The component of the sub-threshold drain current that flows as a result of punch-through is known as punch-through current.
Great efforts have been made and several measures have been taken to prevent short-channel MOSFETs from entering the punch-through regime. Among these measures, implanting dopants under the source/drain extension (SDE) regions proved to be the most reliable and became the most likely used technique for preventing punch-through behavior in field effect transistors. Such implants have been termed “halo” implants.
In the following, a description will be given with reference to FIGS. 1a-1c of a typical prior art process for forming the source and drain regions of a field effect transistor, including a typical “halo” implanting step.
FIG. 1a schematically shows a MOS transistor 100 to be formed on a substrate 1, such as a silicon wafer. Isolation structures 2 define an active region of the transistor 100. Moreover, reference 3 relates to a polysilicon gate electrode of the MOS transistor 100. Reference 6 denotes a gate insulation layer. Finally, references 5′S and 5′D relate to source/drain extensions of the source and drain regions of the MOS transistor 100.
FIG. 1b shows the MOS transistor 100 once halo regions 5h have been formed during a prior art halo implantation step. In particular, in FIG. 1b, references 7a and 7b relate to corresponding angled ion implantation processes to which the substrate 1 is exposed for forming the halo regions 5h. The dopant material implanted during such a process is of the same type as the dopant used in doping the substrate. That is, the halo implants for NMOS and PMOS devices are performed using a P-type and an N-type, respectively, dopant material. In a sense, the halo implants reinforce the dopants in the substrate.
In FIG. 1c, reference 4 relates to dielectric sidewall spacers formed on the sidewalls of the polysilicon line 3 and references 5S and 5D relate to the source and drain regions, respectively, after a further heavy implantation step has been carried out for determining the final concentration of dopants in the source and drain regions.
A typical process flow for forming the transistor 100 as shown in FIG. 1a may include the following steps. Following the formation of the gate insulation layer 6 and the overlying polysilicon line 3 according to well-known lithography techniques, a first ion implantation step is carried out for forming the source/drain extension regions 5′S and 5′D. To this end, a dose of approximately 3×1013 to 3×1014 cm−2 dopant ions is implanted at low energy (30-50 keV). The implantation process causes the edges of these implanted regions to be substantially aligned with the edge of the gate, i.e., this is a self-aligned process. This first ion implantation step is performed with N-type and P-type dopant materials for NMOS and PMOS devices, respectively.
In a next step, as depicted in FIG. 1b, the halo structures 5h are formed. To this end, a further ion implantation step is carried out during which the substrate 1 is exposed to the ion beams 7a and 7b. This halo implant is also self-aligned with the channel edge and dopants are placed beneath those dopants implanted into the SDE regions. As depicted in FIG. 1b, during halo implants, the ion beams 7a and 7b are kept at a tilt angle of approximately 30° with respect to the surface of the substrate 1. In particular, the implanting step is divided into two parts. During the first part, the substrate is exposed to the ion beam 7a and a dose corresponding to one-half of the final dose is implanted. Once the first part is completed, the substrate is rotated 180° about an axis perpendicular to the surface of the substrate and exposed again to the ion beam. In FIG. 1b, two ion beams 7a and 7b have been depicted for reason of clarity; however, the ion beam 7b during the second part corresponds to the ion beam 7a during the first part, with the only difference being that the substrate 1 is rotated 180° once the first part of the implanting step is completed.
The dopant concentration in the regions 5h, as well as the implant energy and the dopants, are selected depending on the type of transistor to be formed on the substrate 1. For instance, boron ions in NMOS and phosphorus in PMOS are implanted to form a halo punch-through suppression region in each device. Usually, phosphorous is implanted at 90 keV with a dose of 2×1013 cm−2 at 25° tilt, in two segments, with the substrate rotated 180° between two segments. Similar procedures are used for implanting boron. A thermal treatment, such as an annealing step, is performed after the ion implantation step for diffusing the dopants into the substrate.
The source and drain regions 5S and 5D of the transistor 100 are then completed during a subsequent step, as depicted in FIG. 1c. In particular, dielectric sidewall spacers 4 are formed on the sidewalls of the polysilicon line 3 according to well-known techniques and a further heavy implantation step is carried out for implanting dopants into those regions of the substrate not covered by the polysilicon line 3 and the sidewall spacers 4. At the end of the heavy implantation step, the source and drain regions 5S and 5D are formed to exhibit the dopant concentration profile depicted in FIG. 1c. For NMOS and PMOS type devices, this heavy implantation step is performed using an N-type and a P-type dopant material, respectively. The manufacturing process is then continued to complete the transistor 100 according to techniques well known to those skilled in the art.
The halo regions 5h allow for the prevention or at least the reduction of the punch-through effect in the transistor 100. However, the dopant concentration in the halo regions 5h, as shown in FIG. 1c, may not be appropriate to adequately prevent or minimize other short-channel effects. For instance, the vertical source/drain extension penetration depth may not be effectively controlled and/or managed adequately, and undesired parasitic substrate currents may arise due to the lower doping in the region of the highest electric field, typically located at the tips 5T of the SDE regions 5′S and 5′D.
Accordingly, in view of the problems explained above, it would be desirable to provide a technique that may solve or reduce one or more of the problems identified above. In particular, it would be desirable to provide a technique that allows the prevention and/or reduction not only of punch-through but of other short-channel effects as well.